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FEATURES High Gain: 200 V/mV typ Single or Dual Supply Operation Input Voltage Range Includes Ground Low Power Consumption (1.5 mW/Comparator) Low Input Bias Current: 100 nA max Low Input Offset Current: 10 nA max Low Offset Voltage: 1 mV max Low Output Saturation Voltage: 250 mV @ 4 mA Logic Output Compatible with TTL, DTL, ECL, MOS and CMOS Directly Replaces LM139/239/339 Comparators Available in Die Form
Quad Low Power, Precision Comparator CMP04
PIN CONNECTIONS 14-Lead Cerdip 14-Lead Plastic DIP 14-Lead SOIC
OUT 2 1 OUT 1 2 V+ 3 IN 1- 4 IN 1+ 5 IN 2- 6 IN 2+ 7
2 3 1 4
14 13 12 11 10 9 8
OUT 3 OUT 4 GND IN 4+ IN 4- IN 3+ IN 3-
CMP04
GENERAL DESCRIPTION
TYPICAL INTERFACE
5.0
Four precision independent comparators comprise the CMP04. Performance highlights include a very low offset voltage, low output saturation voltage and high gain in a single supply design. The input voltage range includes ground for single supply operation and V- for split supplies. A low power supply current of 2 mA, which is independent of supply voltage, makes this the preferred comparator for precision applications requiring minimal power consumption. Maximum logic interface flexibility is offered by the open-collector TTL output.
V+
3
100k
1/4 CD4011
1/4 CMP04
12
Figure 2a. Driving CMOS
5.0 3.5 A 100 A 3.5 A 100 A OUTPUT Q8 Q2 +INPUT Q1 Q3 Q4 Q7 Q5 Q6 -INPUT 3 10k
1/4 CMP04
12 1/4 SN7400
*
*
*SUBSTRATE DIODES
Figure 2b. Driving TTL
Figure 1. Simplified Schematic (1/4 CMP04)
REV. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
CMP04-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter Input Offset Voltage Input Offset Current Input Bias Current Voltage Gain Large-Signal Response Time Small-Signal Response Time Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Saturation Voltage Output Sink Current Output Leakage Current Supply Current Symbol VOS IOS IB AV tr tr CMVR CMRR PSRR VOL ISINK ILEAK I+
(@ V+ = +5 V, TA = +25 C, unless otherwise noted)
Conditions RS = 0 , RL = 5.1 k, VO = 1.4 V IIN(+) - IIN(-), RL = 5.1 k, VO = 1.4 V IIN(+) or IIN(-) RL 15 k, V+ = 15 V2 VIN = TTL Logic Swing, VREF = 1.4 V3 VRL = 5 V, RL = 5.1 k VIN = 100 mV Step3, 5 mV Overdrive VRL = 5 V, RL = 5.1 k (Note 4) (Notes 2, 5) V+ = +5 V to +18 V2 VIN(-) 1 V, VIN(+) = 0, ISINK 4 mA VIN(-) 1 V, VIN(+) = 0, VO 1.5 V VIN(+) 1 V, VIN(-) = 0, VO = 30 V RL = , All Comps V+ = 30 V
1
Min
Typ 0.4 2 25 200 300 1.3
Max 1 10 100
Units mV nA nA V/mV ns s V dB dB mV mA nA mA
80
0 80 80 6
V+ -1.5 100 100 250 16 0.1 0.8
400 100 2.0
NOTES 1 At output switch point, V O = 1.4 V, RS = 0 with V+ from 5 V; and over the full input common-mode range (0 V to V+ -1.5 V). 2 Guaranteed by design. 3 Sample tested. 4 The input common-mode voltage or input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the common-mode voltage range is V+ -1.5 V, but either or both inputs can go to +30 V without damage. 5 RL 15 k, V+ = 15 V, V CM = 1.5 V to 13.5 V. Specifications subject to change without notice.
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .36 V or 18 V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . 36 V dc Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +36 V Operating Temperature Range CMP04BY . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C CMP04FP, FS . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Junction Temperature (TJ) . . . . . . . . . . . . . -65C to +150C Storage Temperature Range . . . . . . . . . . . . -65C to +150C (P Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +125C Input Current (VIN < -3.0 V) . . . . . . . . . . . . . . . . . . . 50 mA Output Short-Circuit to GND . . . . . . . . . . . . . . . . Continuous Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300C
ABSOLUTE MAXIMUM RATINGS 1
Package Type 14-Lead Hermetic DIP (Y) 14-Lead Plastic DIP (P) 14-Lead SOIC
JA
2
JC
Units C/W C/W C/W
94 83 120
10 39 36
NOTES 1 Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 JA is specified for worst case mounting conditions, i.e., JA is specified for device in socket for cerdip and plastic DIP packages; JA is specified for device soldered to printed circuit board for SO package.
ORDERING GUIDE
Model CMP04BY/883C CMP04FP CMP04FS
TA = +25 C VOS 1 mV 1 mV 1 mV
Temperature Ranges -55C to +125C -40C to +85C -40C to +85C
Package Descriptions 14-Lead Cerdip 14-Lead Plastic DIP 14-Lead SOIC
Package Options Q-14 N-14 R-14/SO-14
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the CMP04 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-2-
REV. C
CMP04 ELECTRICAL CHARACTERISTICS CMP04FP/FS, unless otherwise noted)
Parameter Input Offset Voltage Input Offset Current Symbol VOS IOS Conditions RS = 0 , RL = 5.1 k VO = 1.4 V2 IIN(+) - IIN(-) RL = 5.1 k VO = 1.4 V IIN(+) or IIN(-) RL 15 k, V+ = 15 V3 VIN = TTL Logic Swing VREF = 1.4 V4 VRL = 5 V, RL = 5.1 k VIN = 100 mV Step4 5 mV Overdrive VRL = 5 V, RL = 5.1 k (Note 5) (Notes 1, 3) V+ = +5 V to +18 V VIN(-) 1 V, VIN(+) = 0, ISINK 4 mA VIN(-) 1 V, VIN(+) = 0, VO 1.5 V VIN(+) 1 V, VIN(-) = 0, VO = 30 V RL = , All Comps V+ = 30 V 5 5 0 60 80 100 100 250 250 16 16 0.1 0.1 1.2 1.2 200 200 3.0 3.0 700 700 70
(@ V+ = +5 V, -55 C TA +125 C for CMP04BY, -40 C TA +85 C for
CMP04B/F1 Typ 1 1 4 4 4 40 125 300 300 300 1.3 1.3 1.3 V+ -1.5
Min
Max 2 2 20 20 20 200
Units mV mV nA nA nA nA V/mV ns ns ns s s s V dB dB mV mV mA mA nA nA mA mA
Input Bias Current Voltage Gain Large-Signal Response Time
IB AV tr
Small-Signal Response Time
tr
Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Saturation Voltage Output Sink Current Output Leakage Current Supply Current
CMVR CMRR PSRR VOL ISINK ILEAK I+
NOTES 1 RL 15 k, V+ = 15 V, V CM = 1.5 V to 13.5 V. 2 At output switch point, V O = 1.4 V, RS = 0 with V+ from 5 V; and over the full input common-mode range (0 V to V+ -1.5 V). 3 Guaranteed by design. 4 Sample tested. 5 The input common-mode voltage or input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the common-mode voltage range is V+ -1.5 V, but either or both inputs can go to +30 V without damage. Specifications subject to change without notice.
-18V 3.6k
14 13
-18V 3.6k
12 4 1 11 10 9 8
CMP04
2 3
100k 3.6k +18V ONE EACH PER BOARD
1
2
3
4
5
6
7
3.6k +18V
ZENER 5.8V TO 6.2V 1 WATT
470k MIL-STD-883, METHOD 1015, CONDITION B
+30V TO ADJACENT SOCKETS
Figure 3. Burn-In Circuit
REV. C
-3-
CMP04
DICE CHARACTERISTICS
DIE SIZE 0.058 x 0.055 inch, 3190 sq. mils (1.47 x 1.40 mm, 2.058 sq. mm)
WAFER TEST LIMITS
Parameter Input Offset Voltage Input Offset Current
(@ V+ = +5 V, TA = +25 C, unless otherwise noted)
Symbol VOS IOS Conditions RS = 0 , RL = 5.1 k VO = 1.4 V1 IIN(+) - IIN(-) RL = 5.1 k VO = 1.4 V IIN(+) or IIN(-) (Notes 2, 3) (Note 4) V+ = +5 V to +18 V VIN(-) 1 V, VIN(+) = 0, ISINK 4 mA VIN(-) 1 V, VIN(+) = 0, VO 1.5 V VIN(+) 1 V, VIN(-) = 0, VO = 30 V RL = , All Comps V+ = 30 V
1
CMP04N Limit 1
CMP04G Limit 2
Units mV max
10 100 80 V+ -1.5 80 80 400 6 100 2
25 100 50 V+ -1.5 80 80 400 6 100 2
nA max nA max V/mV min V max dB min dB min mV max mA min nA max mA max
Input Bias Current Voltage Gain Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Saturation Voltage Output Sink Current Output Leakage Current Supply Current
IB AV CMVR CMRR PSRR VOL ISINK ILEAK I+
RL 15 k, V+ = 15 V3
NOTES Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS (@ V+ = +5 V, unless otherwise noted)
.
Parameter Large-Signal Response Time
Symbol tr
Conditions VIN = TTL Logic Swing VREF = 1.4 V5 VRL = 5 V, RL = 5.1 k VIN = 100 mV Step 5 mV Overdrive VRL = 5 V, RL = 5.1 k
3 4
CMP04N Typical
CMP04G Typical
Units
600
600
ns
Small-Signal Response Time
tr
5
1.3
1.3
s
NOTES 1 At output switch point, VO = 1.4 V, RS = 0 with V+ from 5 V; and over the full input common-mode range (0 V to V+ -1.5 V). 2 The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the common-mode voltage range is V+ -1.5 V, but either or both inputs can go to +30 V without damage.
Guaranteed by design. RL 15 k. VCM = 1.5 V to 13.5 V. 5 Sample tested. Specifications subject to change without notice.
-4-
REV. C
CMP04 Typical Performance Characteristics
+0.3 IB - INPUT BIAS CURRENT - nA
80
I OS - INPUT OFFSET CURRENT - nA
3.0
VOS - OFFSET VOLTAGE - mV
+0.2
2.0
60 TA = -55 C TA = 0 C 40 TA = +25 C/70 C
+0.1
1.0
0
0
-0.1
TA = +125 C 20
-1.0
-0.2
-2.0
-0.3 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE - C
0 0 5 10 20 25 30 35 15 V+ - SUPPLY VOLTAGE - VDC 40
-3.0 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE - C
Figure 4. Offset Voltage vs. Temperature
Figure 5. Input Bias Current vs. V+ and Temperature
Figure 6. Input Offset Current vs. Temperature
160 150
AV - VOLTAGE GAIN - V/mV
SUPPLY CURRENT - mA
1.1 TA = -55 C 0.9 TA = 0 C
10
VOL - SATURATION VOLTAGE - VDC
OUT OF SATURATION 1.0
140 130 120 110 100 90 80 70 60 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE - C
0.7
TA = +25 C TA = +70 C
TA = +125 C 0.1
0.5
TA = -55 C TA = +25 C
0.3
TA = +125 C
0.01
0.1
0
5
15 10 20 25 30 SUPPLY VOLTAGE - VDC
35
40
0.001 0.01
0.1 1.0 10 IO - OUTPUT SINK CURRENT - mA
100
Figure 7. Voltage Gain vs. Temperature
6.0
Figure 8. Supply Current vs. Supply Voltage
6.0
Figure 9. Output Voltage vs. Output Current and Temperature
OUTPUT VOLTAGE VO - Volts
5.0 4.0 3.0 2.0 1.0 0 0 -50 -100 100mV 20mV
OUTPUT VOLTAGE VO - Volts
INPUT OVERDRIVE = 5.0mV +5VDC VIN 5.1k VOUT
5.0 4.0
INPUT OVERDRIVE = 100mV 20mV
TA = +25 C
3.0 2.0 1.0 0 0 -50 VIN
5mV
+5VDC 5.1k VOUT
INPUT VOLTAGE VIN - mV
TA = +25 C 0 0.5 1.0 TIME - s 1.5 2.0
INPUT VOLTAGE VIN - mV
-100 0 0.5 1.0 TIME - s 1.5 2.0
Figure 10. Response Time for Various Input Overdrives--Negative Transition
Figure 11. Response Time for Various Input Overdrives--Positive Transition
REV. C
-5-
CMP04
TYPICAL APPLICATIONS
V+
+VIN V+ 3k 1M V+ 1M 1M
6.2k
1/4 CMP04 * *OR LOGIC WITHOUT
PULLUP RESISTOR
1/4 CMP04
VO
VO STROBE INPUT
Figure 12. Output Strobing
Figure 15. Inverting Comparator with Hysteresis
V+
2R S +VREF HI
100k
4.3k
1/4 CMP04
+VIN RS
75pF
V+
1/4 CMP04
100k V+ 100k 100k
0 f = 186kHz VO
2R S +VREF LOW
1/4 CMP04
Figure 13. Limit Comparator
Figure 16. Square Wave Oscillator
V+ +VREF 10k +VIN 10M
VIN1
100k
V+ 5.1k
3k
1/4 CMP04
VO
100k VIN2 1N914
1/4 CMP04
VO
Figure 14. Noninverting Comparator with Hysteresis
Figure 17. Comparing Input Voltages of Opposite Polarity
-6-
REV. C
CMP04
V+ V+ 0 V+ R1 1M 10k V+ 1N914 1M 1ms PW R2 100k 80pF D1 1N914 D2 1N914 V+ 15k
t0
100pF
1M
+VIN
1/4 CMP04
0.01 F
t0
VO
t1
0
1M V+ 1M 1N914 1M
1/4 CMP04
1M
t0
t1
t2
0
FOR LARGE RATIOS OF R1/R2, D1 CAN BE OMITTED.
Figure 18. One-Shot Multivibrator
Figure 20. Pulse Generator
V+
V+
39k 100k A V+ B 0 "0" "1" C 100k 1k 100k 1k +0.375V
3k
200k 100k
3k
1/4 CMP04
f
A V+ B 0 100k 100k C
1k
+0.075V
1/4 CMP04
f
1=A*B*C
"0" "1"
1k
1=A+B+C
Figure 19. AND Gate
Figure 21. OR Gate
V+
+4V 1S 0 +VIN
1M 100k 100k
1M 10M
560k 15k
1/4 CMP04
100pF
1/4 CMP04
VO 10M 240k T
V+
t0
t1
0
T = 0.3ms
62k
Figure 22. One-Shot Multivibrator with Input Lockout
REV. C
-7-
CMP04
TYPICAL APPLICATIONS
V+
V+ V3 V2 VC1 V1 0
10k
15k
200k 10k
10M
3.0k V+ 0
V3 51k 10k C1 0.001 F
1/4 CMP04
V+ 3.0k
VO3
t0
t1
t2
t3
t4
10k
10M
V+ V+ 0 +VIN
1/4 CMP04
0
t0
t4
V2 51k 10k
1/4 CMP04
V+ 3.0k
t 0 t2
VO2
INPUT GATING SIGNAL 10M V+ 0
V1 51k
1/4 CMP04
t 0 t1
VO1
Figure 23. Time Delay Generator
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Cerdip (Q-14)
0.005 (0.13) MIN
14
14-Lead Plastic DIP (N-14)
0.795 (20.19) 0.725 (18.42)
14 1 8 7
0.098 (2.49) MAX
8
0.310 (7.87) 0.220 (5.59)
1 7
0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN
PIN 1 0.785 (19.94) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36)
0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN
0.320 (8.13) 0.290 (7.37)
0.210 (5.33) MAX
PIN 1
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
0.100 0.070 (1.78) SEATING (2.54) 0.030 (0.76) PLANE BSC
15 0
0.015 (0.38) 0.008 (0.20)
0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356)
0.100 0.070 (1.77) (2.54) 0.045 (1.15) BSC
SEATING PLANE
0.015 (0.381) 0.008 (0.204)
14-Lead SOIC (R-14)
0.3444 (8.75) 0.3367 (8.55)
14 1 8 7
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
SEATING PLANE
0.0500 (1.27) BSC
0.0192 (0.49) 0.0138 (0.35)
0.0099 (0.25) 0.0075 (0.19)
8 0
0.0500 (1.27) 0.0160 (0.41)
-8-
REV. C
PRINTED IN U.S.A.
C3107a-0-7/98
t0
t3

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